Design and performance of 32-kbit/s π/4-QPSK VLMS MLSE equalizer

Satoshi Denno, Yoichi Saito

Research output: Contribution to journalArticle

Abstract

This article considers an adaptive maximum-likelihood sequence estimation (MLSE) equalizer that can process signals at high speed and discusses its implementation in hardware, together with its performance. The variable-gain least-mean-square (VLMS) algorithm, for which circuit construction is relatively easy, is used for channel estimation. The estimation process is applied to each state to improve tracking performance. The subinterval sampling structure is used to avoid performance deterioration due to the sampling phase. As the first step, pipeline processing for efficient channel estimation and sequence estimation, as well as reduction of computational complexity by avoiding matrix manipulation in the fractional-interval VLMS algorithm, are discussed. The experimentally constructed VLMS-MLSE equalizer can process the air interface for a 384-kbit/s π/4-QPSK signal in real time at 32 kbit/s. It is shown that the floor error in the two-wave Rayleigh fading channel with a delay spread of 500 ns can be reduced to 10-5 or less and that a diversity gain of 5 dB is realized for BER = 10-3. When the experimentally constructed equalizer is applied to a selective diversity receiver system, the same performance is experimentally demonstrated as the theoretical value for delayed detection when there is no delayed wave in the same channel.

Original languageEnglish
Pages (from-to)47-56
Number of pages10
JournalElectronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume83
Issue number5
DOIs
Publication statusPublished - 2000
Externally publishedYes

Keywords

  • Equalizer
  • Fractional interval sampling
  • Hardware
  • High-speed mobile communication
  • MLSE
  • Pipeline processing

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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