Design and implementation of interrupt packaging mechanism

K. Nakashima, S. Kusakabe, H. Taniguchi, M. Amamiya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As the amount of data transferred between the main processing unit and peripheral devices increases, the frequency of interrupts from peripheral devices also increases. Thus, the efficiency of interrupt handling is one of the key issues that must be addressed to realize high performance computing environments. In conventional interrupt mechanisms, an interrupt handler consists of three parts: a pre-processing routine, a main-handler routine and a postprocessing routine. During a pre-processing routine, all register values are pushed to a stack, and values of the interrupt controller are changed so that the main-handler routine can execute with registers in a given interrupt priority. During a post-processing routine, values of interrupt controller are restored, and all register values are popped from the stack. The more interrupts occur, the more preprocessing and post-processing routine overhead must be tolerated In order to reduce interrupt overhead, we propose an interrupt packaging mechanism that packages main handlers of a series of interrupts and reduces the overhead of pre/post-processing. We have designed and implemented the interrupt packaging mechanism for interrupts from a Myrinet NIC (network interface card). In our evaluation, we have improved system performance by 6.07%.

Original languageEnglish
Title of host publicationInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
EditorsKazuki Joe, Alex Veidenbaum
PublisherIEEE Computer Society
Pages95-102
Number of pages8
ISBN (Electronic)0769516351
DOIs
Publication statusPublished - Jan 1 2002
Externally publishedYes
EventInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002 - Big Island, United States
Duration: Jan 11 2002 → …

Publication series

NameProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
Volume2002-January
ISSN (Print)1537-3223

Other

OtherInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
CountryUnited States
CityBig Island
Period1/11/02 → …

Keywords

  • Computer integrated manufacturing
  • Frequency
  • High performance computing
  • Information science
  • Multiprocessor interconnection networks
  • Network interfaces
  • Operating systems
  • Packaging
  • Registers
  • System performance

ASJC Scopus subject areas

  • Hardware and Architecture

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  • Cite this

    Nakashima, K., Kusakabe, S., Taniguchi, H., & Amamiya, M. (2002). Design and implementation of interrupt packaging mechanism. In K. Joe, & A. Veidenbaum (Eds.), International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002 (pp. 95-102). [1035023] (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; Vol. 2002-January). IEEE Computer Society. https://doi.org/10.1109/IWIA.2002.1035023