Composition of dependency graphs for asynchronous circuit synthesis based on synchronous circuit scheduling

Hiroto Kagotani, Takuji Okamoto, Takashi Nanya

Research output: Contribution to journalArticle

Abstract

The results of application of the synchronous circuit scheduling to controlled data flow graph (CDFG) on placing a restriction on the number of usable operators in the circuit are used for specifications in the proposed method for dependency graphs for asynchronous circuit synthesis with the shortest possible execution time. First, in this method, operators are assigned to each operation so that the execution order restriction of the operations by co-use of the operators increases less than it would otherwise. In particular, when conditional branching is involved in the specification, such a branching probability is taken into account. Next, from the binding results, dependency graphs are generated that can be mapped directly to the hardware while the execution sequence restriction of each operation and the conformity of the graphs are taken into account. From the experimental results, it is found that the proposed method functions effectively for the specifications of the actual digital filter and for the hypothetical specifications generated randomly.

Fingerprint

Scheduling
Specifications
Networks (circuits)
Chemical analysis
Data flow graphs
Digital filters
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

@article{5dbdbaf70ba24a9e909c72e7e9407185,
title = "Composition of dependency graphs for asynchronous circuit synthesis based on synchronous circuit scheduling",
abstract = "The results of application of the synchronous circuit scheduling to controlled data flow graph (CDFG) on placing a restriction on the number of usable operators in the circuit are used for specifications in the proposed method for dependency graphs for asynchronous circuit synthesis with the shortest possible execution time. First, in this method, operators are assigned to each operation so that the execution order restriction of the operations by co-use of the operators increases less than it would otherwise. In particular, when conditional branching is involved in the specification, such a branching probability is taken into account. Next, from the binding results, dependency graphs are generated that can be mapped directly to the hardware while the execution sequence restriction of each operation and the conformity of the graphs are taken into account. From the experimental results, it is found that the proposed method functions effectively for the specifications of the actual digital filter and for the hypothetical specifications generated randomly.",
author = "Hiroto Kagotani and Takuji Okamoto and Takashi Nanya",
year = "2000",
doi = "10.1002/1520-6440(200012)83:12<70::AID-ECJC8>3.0.CO;2-9",
language = "English",
volume = "83",
pages = "70--77",
journal = "Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)",
issn = "1042-0967",
publisher = "John Wiley and Sons Inc.",
number = "12",

}

TY - JOUR

T1 - Composition of dependency graphs for asynchronous circuit synthesis based on synchronous circuit scheduling

AU - Kagotani, Hiroto

AU - Okamoto, Takuji

AU - Nanya, Takashi

PY - 2000

Y1 - 2000

N2 - The results of application of the synchronous circuit scheduling to controlled data flow graph (CDFG) on placing a restriction on the number of usable operators in the circuit are used for specifications in the proposed method for dependency graphs for asynchronous circuit synthesis with the shortest possible execution time. First, in this method, operators are assigned to each operation so that the execution order restriction of the operations by co-use of the operators increases less than it would otherwise. In particular, when conditional branching is involved in the specification, such a branching probability is taken into account. Next, from the binding results, dependency graphs are generated that can be mapped directly to the hardware while the execution sequence restriction of each operation and the conformity of the graphs are taken into account. From the experimental results, it is found that the proposed method functions effectively for the specifications of the actual digital filter and for the hypothetical specifications generated randomly.

AB - The results of application of the synchronous circuit scheduling to controlled data flow graph (CDFG) on placing a restriction on the number of usable operators in the circuit are used for specifications in the proposed method for dependency graphs for asynchronous circuit synthesis with the shortest possible execution time. First, in this method, operators are assigned to each operation so that the execution order restriction of the operations by co-use of the operators increases less than it would otherwise. In particular, when conditional branching is involved in the specification, such a branching probability is taken into account. Next, from the binding results, dependency graphs are generated that can be mapped directly to the hardware while the execution sequence restriction of each operation and the conformity of the graphs are taken into account. From the experimental results, it is found that the proposed method functions effectively for the specifications of the actual digital filter and for the hypothetical specifications generated randomly.

UR - http://www.scopus.com/inward/record.url?scp=0033684317&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033684317&partnerID=8YFLogxK

U2 - 10.1002/1520-6440(200012)83:12<70::AID-ECJC8>3.0.CO;2-9

DO - 10.1002/1520-6440(200012)83:12<70::AID-ECJC8>3.0.CO;2-9

M3 - Article

AN - SCOPUS:0033684317

VL - 83

SP - 70

EP - 77

JO - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)

JF - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)

SN - 1042-0967

IS - 12

ER -