Asynchronous PipeRench: Architecture and performance evaluations

H. Kagotani, H. Schmit

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

PipeRench is a configurable architecture that has the unique ability to virtualize an application using dynamic reconfiguration. This paper investigates the potential benefits and costs of implementing this architecture using an asynchronous methodology. Since clock distribution and gating are relatively easy in the synchronous PipeRench, we focus on the benefit due to decreased timing pessimism in an asynchronous implementation. Two architectures for fully asynchronous implementation are considered. PE-based asynchronous implementation yields approximately 80% improvement in performance per stripe. This implementation, however, requires significant increases in configuration storage and wire count. A few particular features of the architecture, such as the crossbar interconnect structure within the stripe, are primarily responsible for this growth in configuration bits and wires. These features, however, are the primary aspects of the PipeRench architecture that make it a good compilation target.

Original languageEnglish
Title of host publicationProceedings - 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages121-129
Number of pages9
ISBN (Electronic)0769519792
DOIs
Publication statusPublished - Jan 1 2003
Event11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003 - Napa, United States
Duration: Apr 9 2003Apr 11 2003

Publication series

NameIEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
Volume2003-January
ISSN (Print)1082-3409

Other

Other11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003
CountryUnited States
CityNapa
Period4/9/034/11/03

Keywords

  • Clocks
  • Computer architecture
  • Fabrics
  • Field programmable gate arrays
  • Logic
  • Microprocessors
  • Power dissipation
  • Registers
  • Timing
  • Wires

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Theoretical Computer Science

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  • Cite this

    Kagotani, H., & Schmit, H. (2003). Asynchronous PipeRench: Architecture and performance evaluations. In Proceedings - 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003 (pp. 121-129). [1227248] (IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPGA.2003.1227248