In this paper, design and organization of bit-serial asynchronous arithmetic circuits on PCA (Plastic Cell Architecture) which is reconfigurable architecture consisting of communicating, memorizing and processing facilities is discussed. Based on the evaluation results of the implementation, a novel architecture of a configurable part of PCA is also proposed. The implementation of bit-serial asynchronous arithmetic circuits does not depend on PCA. Since asynchronous circuits operate with handshaking not with clock signals, different design techniques are required from those adopted in synchronous circuit design. We propose such a new technique for design of multiplier circuit. Furthermore, novel structure for an FIR (Finite Impulse Response) filter, which can also be applied to synchronous implementation, is proposed.