Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs

Yusuke Sugihara, Kimihiro Nanamori, Seiya Ishiwaki, Yuma Hayashi, Kyota Aikawa, Kazuhiro Umetani, Eiji Hiraki, Masayoshi Yamamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

SiC-MOSFETs have attracting increasing attention because of their outstanding characteristics that contributes to high efficiency and high power density of power converters. However, compared to conventional Si-IGBTs, SiC-MOSFETs are susceptible to false triggering, because they tend to generate large switching noise due to ultrafast switching capability and have a lower threshold voltage in high temperature operation. Particularly, disastrous oscillation of repetitive false triggering can occur after a fast turn-off, which is the severe issue for practical application of SiC-MOSFETs. The purpose of this paper is to give an instruction to avoid this phenomenon. This paper hypothesized that the repetitive false triggering is the parasitic oscillation caused by parasitic capacitance of SiC-MOSFET, and parasitic inductance of wiring. Based on this hypothesis, this paper analyzed the oscillatory condition of the parasitic oscillator to propose a design instruction to avoid the oscillatory false triggering. The result revealed that the parasitic inductance of the gate, drain, and source wiring should be designed so that the resonance frequency of the parasitic LC resonator in the gating circuit is far apart from that of the power circuit. This paper also presents experimental results that support appropriateness of the proposed design instruction.

Original languageEnglish
Title of host publication2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages5113-5118
Number of pages6
Volume2017-January
ISBN (Electronic)9781509029983
DOIs
Publication statusPublished - Nov 3 2017
Event9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017 - Cincinnati, United States
Duration: Oct 1 2017Oct 5 2017

Other

Other9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017
CountryUnited States
CityCincinnati
Period10/1/1710/5/17

Fingerprint

MOSFET
Electric wiring
Inductance
High temperature operations
Networks (circuits)
Insulated gate bipolar transistors (IGBT)
Power converters
Threshold voltage
Resonators
Capacitance
Oscillation
Power Converter
Resonance Frequency
Resonator
High Power
High Efficiency
Voltage
Tend
False
Design

Keywords

  • Fast switching
  • Oscillatory false triggering
  • Parasitic inductance
  • Selfsustained oscillation
  • SiC-MOSFET

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Renewable Energy, Sustainability and the Environment
  • Control and Optimization

Cite this

Sugihara, Y., Nanamori, K., Ishiwaki, S., Hayashi, Y., Aikawa, K., Umetani, K., ... Yamamoto, M. (2017). Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs. In 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017 (Vol. 2017-January, pp. 5113-5118). [8096861] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECCE.2017.8096861

Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs. / Sugihara, Yusuke; Nanamori, Kimihiro; Ishiwaki, Seiya; Hayashi, Yuma; Aikawa, Kyota; Umetani, Kazuhiro; Hiraki, Eiji; Yamamoto, Masayoshi.

2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. p. 5113-5118 8096861.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sugihara, Y, Nanamori, K, Ishiwaki, S, Hayashi, Y, Aikawa, K, Umetani, K, Hiraki, E & Yamamoto, M 2017, Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs. in 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. vol. 2017-January, 8096861, Institute of Electrical and Electronics Engineers Inc., pp. 5113-5118, 9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017, Cincinnati, United States, 10/1/17. https://doi.org/10.1109/ECCE.2017.8096861
Sugihara Y, Nanamori K, Ishiwaki S, Hayashi Y, Aikawa K, Umetani K et al. Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs. In 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. Vol. 2017-January. Institute of Electrical and Electronics Engineers Inc. 2017. p. 5113-5118. 8096861 https://doi.org/10.1109/ECCE.2017.8096861
Sugihara, Yusuke ; Nanamori, Kimihiro ; Ishiwaki, Seiya ; Hayashi, Yuma ; Aikawa, Kyota ; Umetani, Kazuhiro ; Hiraki, Eiji ; Yamamoto, Masayoshi. / Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs. 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. pp. 5113-5118
@inproceedings{d7a8d1861f024ca0a6910fc83b164489,
title = "Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs",
abstract = "SiC-MOSFETs have attracting increasing attention because of their outstanding characteristics that contributes to high efficiency and high power density of power converters. However, compared to conventional Si-IGBTs, SiC-MOSFETs are susceptible to false triggering, because they tend to generate large switching noise due to ultrafast switching capability and have a lower threshold voltage in high temperature operation. Particularly, disastrous oscillation of repetitive false triggering can occur after a fast turn-off, which is the severe issue for practical application of SiC-MOSFETs. The purpose of this paper is to give an instruction to avoid this phenomenon. This paper hypothesized that the repetitive false triggering is the parasitic oscillation caused by parasitic capacitance of SiC-MOSFET, and parasitic inductance of wiring. Based on this hypothesis, this paper analyzed the oscillatory condition of the parasitic oscillator to propose a design instruction to avoid the oscillatory false triggering. The result revealed that the parasitic inductance of the gate, drain, and source wiring should be designed so that the resonance frequency of the parasitic LC resonator in the gating circuit is far apart from that of the power circuit. This paper also presents experimental results that support appropriateness of the proposed design instruction.",
keywords = "Fast switching, Oscillatory false triggering, Parasitic inductance, Selfsustained oscillation, SiC-MOSFET",
author = "Yusuke Sugihara and Kimihiro Nanamori and Seiya Ishiwaki and Yuma Hayashi and Kyota Aikawa and Kazuhiro Umetani and Eiji Hiraki and Masayoshi Yamamoto",
year = "2017",
month = "11",
day = "3",
doi = "10.1109/ECCE.2017.8096861",
language = "English",
volume = "2017-January",
pages = "5113--5118",
booktitle = "2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs

AU - Sugihara, Yusuke

AU - Nanamori, Kimihiro

AU - Ishiwaki, Seiya

AU - Hayashi, Yuma

AU - Aikawa, Kyota

AU - Umetani, Kazuhiro

AU - Hiraki, Eiji

AU - Yamamoto, Masayoshi

PY - 2017/11/3

Y1 - 2017/11/3

N2 - SiC-MOSFETs have attracting increasing attention because of their outstanding characteristics that contributes to high efficiency and high power density of power converters. However, compared to conventional Si-IGBTs, SiC-MOSFETs are susceptible to false triggering, because they tend to generate large switching noise due to ultrafast switching capability and have a lower threshold voltage in high temperature operation. Particularly, disastrous oscillation of repetitive false triggering can occur after a fast turn-off, which is the severe issue for practical application of SiC-MOSFETs. The purpose of this paper is to give an instruction to avoid this phenomenon. This paper hypothesized that the repetitive false triggering is the parasitic oscillation caused by parasitic capacitance of SiC-MOSFET, and parasitic inductance of wiring. Based on this hypothesis, this paper analyzed the oscillatory condition of the parasitic oscillator to propose a design instruction to avoid the oscillatory false triggering. The result revealed that the parasitic inductance of the gate, drain, and source wiring should be designed so that the resonance frequency of the parasitic LC resonator in the gating circuit is far apart from that of the power circuit. This paper also presents experimental results that support appropriateness of the proposed design instruction.

AB - SiC-MOSFETs have attracting increasing attention because of their outstanding characteristics that contributes to high efficiency and high power density of power converters. However, compared to conventional Si-IGBTs, SiC-MOSFETs are susceptible to false triggering, because they tend to generate large switching noise due to ultrafast switching capability and have a lower threshold voltage in high temperature operation. Particularly, disastrous oscillation of repetitive false triggering can occur after a fast turn-off, which is the severe issue for practical application of SiC-MOSFETs. The purpose of this paper is to give an instruction to avoid this phenomenon. This paper hypothesized that the repetitive false triggering is the parasitic oscillation caused by parasitic capacitance of SiC-MOSFET, and parasitic inductance of wiring. Based on this hypothesis, this paper analyzed the oscillatory condition of the parasitic oscillator to propose a design instruction to avoid the oscillatory false triggering. The result revealed that the parasitic inductance of the gate, drain, and source wiring should be designed so that the resonance frequency of the parasitic LC resonator in the gating circuit is far apart from that of the power circuit. This paper also presents experimental results that support appropriateness of the proposed design instruction.

KW - Fast switching

KW - Oscillatory false triggering

KW - Parasitic inductance

KW - Selfsustained oscillation

KW - SiC-MOSFET

UR - http://www.scopus.com/inward/record.url?scp=85041368665&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85041368665&partnerID=8YFLogxK

U2 - 10.1109/ECCE.2017.8096861

DO - 10.1109/ECCE.2017.8096861

M3 - Conference contribution

AN - SCOPUS:85041368665

VL - 2017-January

SP - 5113

EP - 5118

BT - 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -