An optically differential reconfigurable gate array with a dynamic reconfiguration circuit

Minoru Watanabe, Fuminori Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

An optically differential reconfigurable gate array (ODRGA) using a dynamic circuit technique is proposed to reduce the area occupied by the configuration circuit on a VLSI chip. The ODRGA reconfiguration process is performed by calculating the difference between previous configuration data stored on a VLSI chip and subsequent optically-supplied configuration data. The reconfiguration circuit of our previously proposed ODRGA using static circuit techniques required a large implementation area. This paper introduces a new dynamic reconfiguration circuit and compares an estimate of its area on the VLSI chip with that obtained by the static technique.

Original languageEnglish
Title of host publicationProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages4-7
Number of pages4
ISBN (Electronic)0769519261, 9780769519265
DOIs
Publication statusPublished - 2003
Externally publishedYes
EventInternational Parallel and Distributed Processing Symposium, IPDPS 2003 - Nice, France
Duration: Apr 22 2003Apr 26 2003

Publication series

NameProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Conference

ConferenceInternational Parallel and Distributed Processing Symposium, IPDPS 2003
Country/TerritoryFrance
CityNice
Period4/22/034/26/03

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computational Theory and Mathematics
  • Software

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