An Optically Differential Reconfigurable Gate Array (ODRGA) is a type of Field Programmable Gate Array (FPGA), but its gate array can be reconfigured optically in less than 6 ns. We have fabricated a 68 gate-count ODRGA. However, optical differential reconfiguration circuits, which are capable of optical detection of configuration contexts and which can support reconfiguration of an arbitrary part of its gate array bit-by-bit, occupy up to 47% of the implementation area of ODRGA-VLSI chip and prevent realization of a high gate-count ODRGA. Therefore, a dynamic optical differential reconfiguration circuit was developed to reduce the implementation area of optical reconfiguration circuits. It has been evaluated separately. This paper presents the first 476 gate count ODRGA-VLSI chip with a standard 0.35 μm 3-metal CMOS process technology using an improved dynamic optical differential reconfiguration circuit. In addition, the dynamic reconfiguration frequency and performance of logic blocks are shown using HSPICE simulation results. Finally, this paper presents an estimation of the use of a standard 0.35 μm 3-metal 14.2 × 14.2 mm chip.