An efficient implementation method of a metric computation accelerator for fractal image compression using reconfigurable hardware

Hidehisa Naganq, Akihiro Matsuura, Akira Nagoya

Research output: Contribution to journalArticle

Abstract

This paper proposes a method for implementing a metric computation accelerator for fractal image compression using reconfigurable hardware. The most time-consuming part in the encoding of this compression is computation of metrics among image blocks. In our method, each processing element (PE) configured for an image block accelerates these computations by pipeline processing. Furthermore, by configuring the PE for a specific image block, we can reduce the number of adders, which are the main computing elements, by a half even in the worst case.

Original languageEnglish
Pages (from-to)372-377
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE84-A
Issue number1
Publication statusPublished - Jan 2001
Externally publishedYes

Keywords

  • Fractal image compression
  • Metric computation
  • Pipeline processing
  • Reconfigurable hardware

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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