TY - GEN
T1 - An acceleration and optimization method for optical reconfiguration
AU - Watanabe, Minoru
AU - Yamaguchi, Naoki
PY - 2008
Y1 - 2008
N2 - Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However, such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs' reconfiguration frequency without the necessity for any increase of laser power. This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.
AB - Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However, such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs' reconfiguration frequency without the necessity for any increase of laser power. This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.
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U2 - 10.1109/VLSI.2008.26
DO - 10.1109/VLSI.2008.26
M3 - Conference contribution
AN - SCOPUS:47649105466
SN - 0769530834
SN - 9780769530833
T3 - Proceedings of the IEEE International Frequency Control Symposium and Exposition
SP - 607
EP - 612
BT - Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008
T2 - 21st International Conference on VLSI Design, VLSI DESIGN 2008
Y2 - 4 January 2008 through 8 January 2008
ER -