An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A zero-overhead dynamic optically reconfigurable gate array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize both a high gate-count and zero-overhead rapid reconfiguration. This paper presents the world's largest 11,424 gate-count zero-overhead VLSI chip fabricated on a 96.04 mm2 chip using 0.35 μm-3 metal CMOS process technology. The optical reconfiguration circuit, the gate array structure, the CAD layout, and the performance of ZO-DORGA-VLSI are described, with reference to experimental results related to the reconfiguration period and retention time.

Original languageEnglish
Title of host publicationProceedings - 20th Anniversary IEEE International SOC Conference
Pages75-78
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan, Province of China
Duration: Sep 26 2007Sep 29 2007

Publication series

NameProceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference20th Anniversary IEEE International SOC Conference
Country/TerritoryTaiwan, Province of China
CityHsinchu
Period9/26/079/29/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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