Abstract
The problems faced in the automatic synthesis of hardware from operation descriptions are the scheduling problem and the allocation problem. The allocation problem can be further divided into three interrelated subproblems. In this paper, we propose an approximation algorithm that applies a hybrid of a greedy algorithm and a genetic algorithm (GA) to the data transfer binding problem. This algorithm uses a maximum weighted clique algorithm to search for the transfer destinations that can be shared by a selector and a GA to search for the bus allocation for the transfer data for general bus-oriented interconnections. This GA searches for a highly accurate solution in real time by using three greedy algorithms to generate the initial population and conducting a local search when the children are generated. The evaluation of the performance using eight problems showed that although the computation time was worse than that of a conventional algorithm, the proposed algorithm yielded a much more accurate solut ion.
Original language | English |
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Pages (from-to) | 13-22 |
Number of pages | 10 |
Journal | Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi) |
Volume | 84 |
Issue number | 5 |
DOIs | |
Publication status | Published - Jul 10 2001 |
Externally published | Yes |
Keywords
- Automatic hardware synthesis
- Bus-oriented interconnections
- Data transfer binding problem
- Genetic algorithm
- Greedy algorithm
ASJC Scopus subject areas
- Electrical and Electronic Engineering