### Abstract

A parallel algorithm for channel routing problems is presented in this paper. The channel routing problem is very important in the automatic layout design of VLSI circuits and printed circuit boards. The problem is to route the given interconnections between two rows of terminals on a multilayer channel where the channel area must be minimized. Although several algorithms have been proposed for two-layer problems, two-Iayer-and-over-the-cell problems, and three-layer problems, the current advancement of VLSI chip technology allows us to use four layers composed of two metal layers and two polysilicon layers for routing in a chip. The goal of the proposed parallel algorithm is to find the near-optimum routing solution for the given interconnections in a short time. The algorithm is applied for the four-layer channel routing problems where it requires n × m × 2 processing elements for the n-netm-track problem. The algorithm has three advantages over the conventional algorithms: 1) it can be easily modified for accommodating more than four-layer problems, 2) it runs not only on a sequential machine but also on a parallel machine with maximally n ×m × 2 processors, and 3) the program size is very small. The algorithm is verified by solving seven benchmark problems where the algorithm finds routing solutions in a nearly constant time with n × m × 2 processors.

Original language | English |
---|---|

Pages (from-to) | 464-474 |

Number of pages | 11 |

Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Volume | 11 |

Issue number | 4 |

DOIs | |

Publication status | Published - 1992 |

Externally published | Yes |

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### ASJC Scopus subject areas

- Computer Graphics and Computer-Aided Design
- Software
- Electrical and Electronic Engineering
- Computational Theory and Mathematics
- Computer Science Applications
- Hardware and Architecture

### Cite this

*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*,

*11*(4), 464-474. https://doi.org/10.1109/43.125094

**A Parallel Algorithm for Channel Routing Problems.** / Funabiki, Nobuo; Funabiki, Nobuo; Takefuji, Yoshiyasu.

Research output: Contribution to journal › Article

*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, vol. 11, no. 4, pp. 464-474. https://doi.org/10.1109/43.125094

}

TY - JOUR

T1 - A Parallel Algorithm for Channel Routing Problems

AU - Funabiki, Nobuo

AU - Funabiki, Nobuo

AU - Takefuji, Yoshiyasu

PY - 1992

Y1 - 1992

N2 - A parallel algorithm for channel routing problems is presented in this paper. The channel routing problem is very important in the automatic layout design of VLSI circuits and printed circuit boards. The problem is to route the given interconnections between two rows of terminals on a multilayer channel where the channel area must be minimized. Although several algorithms have been proposed for two-layer problems, two-Iayer-and-over-the-cell problems, and three-layer problems, the current advancement of VLSI chip technology allows us to use four layers composed of two metal layers and two polysilicon layers for routing in a chip. The goal of the proposed parallel algorithm is to find the near-optimum routing solution for the given interconnections in a short time. The algorithm is applied for the four-layer channel routing problems where it requires n × m × 2 processing elements for the n-netm-track problem. The algorithm has three advantages over the conventional algorithms: 1) it can be easily modified for accommodating more than four-layer problems, 2) it runs not only on a sequential machine but also on a parallel machine with maximally n ×m × 2 processors, and 3) the program size is very small. The algorithm is verified by solving seven benchmark problems where the algorithm finds routing solutions in a nearly constant time with n × m × 2 processors.

AB - A parallel algorithm for channel routing problems is presented in this paper. The channel routing problem is very important in the automatic layout design of VLSI circuits and printed circuit boards. The problem is to route the given interconnections between two rows of terminals on a multilayer channel where the channel area must be minimized. Although several algorithms have been proposed for two-layer problems, two-Iayer-and-over-the-cell problems, and three-layer problems, the current advancement of VLSI chip technology allows us to use four layers composed of two metal layers and two polysilicon layers for routing in a chip. The goal of the proposed parallel algorithm is to find the near-optimum routing solution for the given interconnections in a short time. The algorithm is applied for the four-layer channel routing problems where it requires n × m × 2 processing elements for the n-netm-track problem. The algorithm has three advantages over the conventional algorithms: 1) it can be easily modified for accommodating more than four-layer problems, 2) it runs not only on a sequential machine but also on a parallel machine with maximally n ×m × 2 processors, and 3) the program size is very small. The algorithm is verified by solving seven benchmark problems where the algorithm finds routing solutions in a nearly constant time with n × m × 2 processors.

UR - http://www.scopus.com/inward/record.url?scp=0026850506&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026850506&partnerID=8YFLogxK

U2 - 10.1109/43.125094

DO - 10.1109/43.125094

M3 - Article

AN - SCOPUS:0026850506

VL - 11

SP - 464

EP - 474

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 4

ER -