A low-complexity hardware implementation of compressed sensing-based channel estimation for ISDB-T system

Rian Ferdian, Yafei Hou, Minoru Okada

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Compressed sensing (CS) is one of the hottest research topics in the sparse signal reconstruction problem. But CS implementation has a drawback of high computational complexity due to calculation between large size of matrices. In this paper, we will propose a low-complexity CS hardware realization for channel estimation in the integrated services digital broadcasting-terrestrial (ISDB-T) system using several optimization methods to reduce the implementation complexity of CS usage. Since the ISDB-T is based on orthogonal frequency division and multiplexing system, the measurement matrix of CS computation is a truncated discrete Fourier transform (DFT) matrix. We can exploit the symmetrical property of this DFT matrix to significantly reduce its multiplication complexity and random access memory usage. To achieve fast reconstruction period, this paper also provides a hardware architecture for the proposed method and its realization in field programmable gate array. The simulation results show that the proposed methods can achieve lower complexity CS-based channel estimation with almost the identical system performance with the conventional method. Moreover, the realized hardware can achieve the fastest execution time compare to that of other existing methods.

Original languageEnglish
Article number7637036
Pages (from-to)92-102
Number of pages11
JournalIEEE Transactions on Broadcasting
Volume63
Issue number1
DOIs
Publication statusPublished - Mar 1 2017
Externally publishedYes

Keywords

  • Channel estimation
  • compressed sensing
  • FPGA implementation
  • ISDB-T
  • orthogonal matching pursuit

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

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