A gradual neural network approach for FPGA segmented channel routing problems

Nobuo Funabiki, Makiko Yoda, Junji Kitamichi, Seishi Nishikawa

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

A novel neural network approach called gradual neural network (GNN) is presented for segmented channel routing in field programmable gate arrays (FPGA's). FPGA's contain predefined segmented channels for net routing, where adjacent segments in a track can be interconnected through programmable switches for longer segments. The goal of the FPGA segmented channel routing problem, known to be NP-complete, is to find a conflict-free net routing with the minimum routing cost. The GNN for the N-net-M-track problem consists of a neural network of N x M binary neurons and a gradual expansion scheme. The neural network satisfies the constraints of the problem, while the gradual expansion scheme seeks the cost minimization by gradually increasing activated neurons. The energy function and the motion equation are newly defined with heuristic methods. The performance is verified through solving 30 instances, where GNN finds better solutions than existing algorithms within a constant number of iteration steps.

Original languageEnglish
Pages (from-to)481-489
Number of pages9
JournalIEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Volume29
Issue number4
DOIs
Publication statusPublished - Aug 1999
Externally publishedYes

Fingerprint

Field programmable gate arrays (FPGA)
Neural networks
Neurons
Heuristic methods
Equations of motion
Costs
Switches

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Artificial Intelligence
  • Human-Computer Interaction

Cite this

A gradual neural network approach for FPGA segmented channel routing problems. / Funabiki, Nobuo; Yoda, Makiko; Kitamichi, Junji; Nishikawa, Seishi.

In: IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics, Vol. 29, No. 4, 08.1999, p. 481-489.

Research output: Contribution to journalArticle

@article{219c4b7a47564fd48c385184e38c8302,
title = "A gradual neural network approach for FPGA segmented channel routing problems",
abstract = "A novel neural network approach called gradual neural network (GNN) is presented for segmented channel routing in field programmable gate arrays (FPGA's). FPGA's contain predefined segmented channels for net routing, where adjacent segments in a track can be interconnected through programmable switches for longer segments. The goal of the FPGA segmented channel routing problem, known to be NP-complete, is to find a conflict-free net routing with the minimum routing cost. The GNN for the N-net-M-track problem consists of a neural network of N x M binary neurons and a gradual expansion scheme. The neural network satisfies the constraints of the problem, while the gradual expansion scheme seeks the cost minimization by gradually increasing activated neurons. The energy function and the motion equation are newly defined with heuristic methods. The performance is verified through solving 30 instances, where GNN finds better solutions than existing algorithms within a constant number of iteration steps.",
author = "Nobuo Funabiki and Makiko Yoda and Junji Kitamichi and Seishi Nishikawa",
year = "1999",
month = "8",
doi = "10.1109/3477.775264",
language = "English",
volume = "29",
pages = "481--489",
journal = "IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics",
issn = "1083-4419",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - A gradual neural network approach for FPGA segmented channel routing problems

AU - Funabiki, Nobuo

AU - Yoda, Makiko

AU - Kitamichi, Junji

AU - Nishikawa, Seishi

PY - 1999/8

Y1 - 1999/8

N2 - A novel neural network approach called gradual neural network (GNN) is presented for segmented channel routing in field programmable gate arrays (FPGA's). FPGA's contain predefined segmented channels for net routing, where adjacent segments in a track can be interconnected through programmable switches for longer segments. The goal of the FPGA segmented channel routing problem, known to be NP-complete, is to find a conflict-free net routing with the minimum routing cost. The GNN for the N-net-M-track problem consists of a neural network of N x M binary neurons and a gradual expansion scheme. The neural network satisfies the constraints of the problem, while the gradual expansion scheme seeks the cost minimization by gradually increasing activated neurons. The energy function and the motion equation are newly defined with heuristic methods. The performance is verified through solving 30 instances, where GNN finds better solutions than existing algorithms within a constant number of iteration steps.

AB - A novel neural network approach called gradual neural network (GNN) is presented for segmented channel routing in field programmable gate arrays (FPGA's). FPGA's contain predefined segmented channels for net routing, where adjacent segments in a track can be interconnected through programmable switches for longer segments. The goal of the FPGA segmented channel routing problem, known to be NP-complete, is to find a conflict-free net routing with the minimum routing cost. The GNN for the N-net-M-track problem consists of a neural network of N x M binary neurons and a gradual expansion scheme. The neural network satisfies the constraints of the problem, while the gradual expansion scheme seeks the cost minimization by gradually increasing activated neurons. The energy function and the motion equation are newly defined with heuristic methods. The performance is verified through solving 30 instances, where GNN finds better solutions than existing algorithms within a constant number of iteration steps.

UR - http://www.scopus.com/inward/record.url?scp=0033177473&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033177473&partnerID=8YFLogxK

U2 - 10.1109/3477.775264

DO - 10.1109/3477.775264

M3 - Article

VL - 29

SP - 481

EP - 489

JO - IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics

JF - IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics

SN - 1083-4419

IS - 4

ER -