A fast bit loading algorithm synchronized with commercial power supply for in-home PLC systems

Shinya Honda, Daisuke Umehara, Taro Hayasaki, Satoshi Denno, Masahiro Morikura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)

Abstract

In-home PLC (Power Line Communication) is one of the most attractive in-home networkings. However, there are a lot of technical issues for the realization of PLC with high rate and high reliability. These issues include the influence of frequency selective and linear periodically time-variant (LPTV) channel synchronized with commercial power supply. In particular, we show that some kind of switching power devices impact deep and deterministic time selectivity for power line channels. The combination of OFDM (Orthogonal Frequency Division Multiplexing) and bit loading algorithm is a powerful tool to increase the bit rate or reliability for quasi-static frequency selective channels including power line channels. However, a quick response will be required for the execution of bit loading algorithm since power line channels are synchronized with commercial power supply. In this paper, we propose a fast bit loading algorithm based on the fractional knapsack algorithm to enhance the bit rate under the condition that the transmitted power is constant. Furthermore, we evaluate the achievable bit rate of the proposed algorithm for the SNR over a power line channel and compare it with the achievable bit rate based on water filling theory.

Original languageEnglish
Title of host publicationIEEE ISPLC 2008 - 2008 IEEE International Symposium on Power Line Communications and Its Applications
Pages336-341
Number of pages6
DOIs
Publication statusPublished - Sep 12 2008
Externally publishedYes
Event2008 IEEE International Symposium on Power Line Communications and Its Applications, IEEE ISPLC 2008 - Jeju Island, Korea, Republic of
Duration: Apr 2 2008Apr 4 2008

Publication series

NameIEEE ISPLC 2008 - 2008 IEEE International Symposium on Power Line Communications and Its Applications

Other

Other2008 IEEE International Symposium on Power Line Communications and Its Applications, IEEE ISPLC 2008
CountryKorea, Republic of
CityJeju Island
Period4/2/084/4/08

Keywords

  • Bit loading algorithm
  • Fractional knapsack algorithm
  • LPTV channel
  • OFDM
  • Power line communication
  • Water filling theory

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Communication

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    Honda, S., Umehara, D., Hayasaki, T., Denno, S., & Morikura, M. (2008). A fast bit loading algorithm synchronized with commercial power supply for in-home PLC systems. In IEEE ISPLC 2008 - 2008 IEEE International Symposium on Power Line Communications and Its Applications (pp. 336-341). [4510450] (IEEE ISPLC 2008 - 2008 IEEE International Symposium on Power Line Communications and Its Applications). https://doi.org/10.1109/ISPLC.2008.4510450