TY - GEN
T1 - A 16-context optically reconfigurable gate array
AU - Nakajima, Mao
AU - Watanabe, Minoru
PY - 2009
Y1 - 2009
N2 - Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the fastest 317-657 ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.
AB - Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the fastest 317-657 ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.
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U2 - 10.1109/ASAP.2009.41
DO - 10.1109/ASAP.2009.41
M3 - Conference contribution
AN - SCOPUS:71049135282
SN - 9780769537320
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 227
EP - 230
BT - Proceedings - 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009
T2 - 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009
Y2 - 7 July 2009 through 9 July 2009
ER -