A 140 GHz area-and-power-efficient VCO using frequency doubler in 65nm CMOS

Yoshitaka Otsuki, Daisuke Yamazaki, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka

Research output: Contribution to journalArticle

Abstract

This paper presents a compact, low-phase-noise and low-power D-band VCO with the tuning range from 140.1 to 143.5 GHz. To improve the area and power efficiency, we avoid using signal amplification and matching circuits in the VCO, where a 70GHz LC oscillator is directly coupled to a frequency doubler. The layout of the transistors is optimized so that the signal loss and reflection are minimized. The proposed VCO fabricated in a 65 nm CMOS technology occupies the core area of 0.05mm2. It achieves the output power of -8 dBm and the phase noise of -108.2 dBc/Hz at 10MHz offset with the power consumption of 24mW from 1V supply, which leads to the figure-of-merit (FoM) of -177.4 dBc/Hz.

Original languageEnglish
Article number20190051
JournalIEICE Electronics Express
Volume16
Issue number6
DOIs
Publication statusPublished - Jan 1 2019
Externally publishedYes

Fingerprint

Frequency doublers
voltage controlled oscillators
Variable frequency oscillators
CMOS
Phase noise
power efficiency
figure of merit
layouts
Amplification
Transistors
Electric power utilization
transistors
Tuning
tuning
oscillators
Networks (circuits)
output

Keywords

  • CMOs
  • D-band
  • Frequency doubler
  • Millimeterwave silicon rfics
  • Voltage-controlled oscillator (VCO)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

A 140 GHz area-and-power-efficient VCO using frequency doubler in 65nm CMOS. / Otsuki, Yoshitaka; Yamazaki, Daisuke; Khanh, Nguyen Ngoc Mai; Iizuka, Tetsuya.

In: IEICE Electronics Express, Vol. 16, No. 6, 20190051, 01.01.2019.

Research output: Contribution to journalArticle

Otsuki, Yoshitaka ; Yamazaki, Daisuke ; Khanh, Nguyen Ngoc Mai ; Iizuka, Tetsuya. / A 140 GHz area-and-power-efficient VCO using frequency doubler in 65nm CMOS. In: IEICE Electronics Express. 2019 ; Vol. 16, No. 6.
@article{086e8db36bcd444ab0afcc10837bd457,
title = "A 140 GHz area-and-power-efficient VCO using frequency doubler in 65nm CMOS",
abstract = "This paper presents a compact, low-phase-noise and low-power D-band VCO with the tuning range from 140.1 to 143.5 GHz. To improve the area and power efficiency, we avoid using signal amplification and matching circuits in the VCO, where a 70GHz LC oscillator is directly coupled to a frequency doubler. The layout of the transistors is optimized so that the signal loss and reflection are minimized. The proposed VCO fabricated in a 65 nm CMOS technology occupies the core area of 0.05mm2. It achieves the output power of -8 dBm and the phase noise of -108.2 dBc/Hz at 10MHz offset with the power consumption of 24mW from 1V supply, which leads to the figure-of-merit (FoM) of -177.4 dBc/Hz.",
keywords = "CMOs, D-band, Frequency doubler, Millimeterwave silicon rfics, Voltage-controlled oscillator (VCO)",
author = "Yoshitaka Otsuki and Daisuke Yamazaki and Khanh, {Nguyen Ngoc Mai} and Tetsuya Iizuka",
year = "2019",
month = "1",
day = "1",
doi = "10.1587/elex.16.20190051",
language = "English",
volume = "16",
journal = "IEICE Electronics Express",
issn = "1349-2543",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "6",

}

TY - JOUR

T1 - A 140 GHz area-and-power-efficient VCO using frequency doubler in 65nm CMOS

AU - Otsuki, Yoshitaka

AU - Yamazaki, Daisuke

AU - Khanh, Nguyen Ngoc Mai

AU - Iizuka, Tetsuya

PY - 2019/1/1

Y1 - 2019/1/1

N2 - This paper presents a compact, low-phase-noise and low-power D-band VCO with the tuning range from 140.1 to 143.5 GHz. To improve the area and power efficiency, we avoid using signal amplification and matching circuits in the VCO, where a 70GHz LC oscillator is directly coupled to a frequency doubler. The layout of the transistors is optimized so that the signal loss and reflection are minimized. The proposed VCO fabricated in a 65 nm CMOS technology occupies the core area of 0.05mm2. It achieves the output power of -8 dBm and the phase noise of -108.2 dBc/Hz at 10MHz offset with the power consumption of 24mW from 1V supply, which leads to the figure-of-merit (FoM) of -177.4 dBc/Hz.

AB - This paper presents a compact, low-phase-noise and low-power D-band VCO with the tuning range from 140.1 to 143.5 GHz. To improve the area and power efficiency, we avoid using signal amplification and matching circuits in the VCO, where a 70GHz LC oscillator is directly coupled to a frequency doubler. The layout of the transistors is optimized so that the signal loss and reflection are minimized. The proposed VCO fabricated in a 65 nm CMOS technology occupies the core area of 0.05mm2. It achieves the output power of -8 dBm and the phase noise of -108.2 dBc/Hz at 10MHz offset with the power consumption of 24mW from 1V supply, which leads to the figure-of-merit (FoM) of -177.4 dBc/Hz.

KW - CMOs

KW - D-band

KW - Frequency doubler

KW - Millimeterwave silicon rfics

KW - Voltage-controlled oscillator (VCO)

UR - http://www.scopus.com/inward/record.url?scp=85065532656&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85065532656&partnerID=8YFLogxK

U2 - 10.1587/elex.16.20190051

DO - 10.1587/elex.16.20190051

M3 - Article

AN - SCOPUS:85065532656

VL - 16

JO - IEICE Electronics Express

JF - IEICE Electronics Express

SN - 1349-2543

IS - 6

M1 - 20190051

ER -