• 305 Citations
  • 8 h-Index
1987 …2018

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2011

PARTHENONの概要

Nagoya, A., 2011, In : 第17回PARTHENON講習会資料(CD-R). p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2011, In : 第17回PARTHENON講習会資料(CD-R). p. 1-24 24 p.

Research output: Contribution to journalArticle

2008

PARTHENONの概要

Nagoya, A., 2008, In : 第16回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2008, In : 第16回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

2007

Network processor for high-speed network and quick programming

Murooka, T., Nagoya, A., Miyazaki, T., Ochi, H. & Nakamura, Y., Feb 1 2007, In : Journal of Circuits, Systems and Computers. 16, 1, p. 65-79 15 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2007, In : 第15回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2007, In : 第15回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

2006

PARTHENONの概要

Nagoya, A., 2006, In : 第14回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2006, In : 第14回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

自律再構成可能アーキテクチャPCAの構成手法

Nagoya, A., 2006, In : 電子情報通信学会論文誌 D. J89-D, 6, p. 1110-1119 10 p.

Research output: Contribution to journalArticle

2005

PARTHENONの概要

Nagoya, A., 2005, In : 第12回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2005, In : 第12回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

Dynamically reconfigurable logic LSI: PCA-2

Ito, H., Konishi, R., Nakada, H., Tsuboi, H., Okuyama, Y. & Nagoya, A., Aug 2004, In : IEICE Transactions on Information and Systems. E87-D, 8, p. 2011-2020 10 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

PARTHENONの概要

Nagoya, A., 2004, In : 第12回PARTHENON講習会テキスト. p. 85-96 12 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2004, In : 第12回PARTHENON講習会テキスト. p. 97-122 26 p.

Research output: Contribution to journalArticle

2003

Dynamically Reconfigurable Logic LSI designed as Fully Asynchronous System - PCA-2

Nagoya, A., 2003, In : Proc. of COOL Chips VI. p. 84-84 1 p.

Research output: Contribution to journalArticle

Dynamically Reconfigurable Logic LSI - PCA-1: The First Realization of the Plastic Cell Architecture

Ito, H., Konishi, R., Nakada, H., Oguri, K., Inamori, M. & Nagoya, A., May 2003, In : IEICE Transactions on Information and Systems. E86-D, 5, p. 859-867 9 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

PARTHENONの概要

Nagoya, A., 2003, In : 第11回PARTHENON講習会テキスト. p. 129-140 12 p.

Research output: Contribution to journalArticle

Solving satisfiability problems by using reconfigurable hardware

Suyama, T., Yokoo, M., Sawada, H. & Nagoya, A., Mar 1 2003, In : Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi). 86, 3, p. 35-46 12 p.

Research output: Contribution to journalArticle

2002

A method of mapping finite state machine into PCA plastic parts

Inamori, M., Nakada, H., Konishi, R., Nagoya, A. & Oguri, K., Apr 2002, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 4, p. 804-810 7 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

A new notion for functional flexibility: A summary

Yamashita, S., Sawada, H. & Nagoya, A., Dec 1 2002, In : IEEE Circuits and Systems Magazine. 2, 2, p. 52-54 3 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2002, In : 第10回PARTHENON講習会テキスト. p. 3-14 12 p.

Research output: Contribution to journalArticle

“SPFD: A New Method to Express Functional Flexibility”

Yamashita, S., Sawada, H. & Nagoya, A., 2002, In : IEEE Circuits and Systems Magazine. 2, 2, p. 53 1 p.

Research output: Contribution to journalArticle

2001

A general framework to use various decomposition methods for LUT network synthesis

Yamashita, S., Sawada, H. & Nagoya, A., Nov 2001, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2915-2922 8 p.

Research output: Contribution to journalArticle

Solving satisfiability problems using reconfigurable computing

Suyama, T., Yokoo, M., Sawada, H. & Nagoya, A., Feb 1 2001, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9, 1, p. 109-116 8 p.

Research output: Contribution to journalArticle

32 Citations (Scopus)
2000

Concept of the Plastic Cell Architecture (PCA)

Nagoya, A. & Oguri, K., Jan 1 2000, In : NTT R and D. 49, 9, p. 513-517 5 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Efficient kernel generation based on implicit cube set representations and its applications

Sawada, H., Yamashita, S. & Nagoya, A., Dec 1 2000, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2513-2519 7 p.

Research output: Contribution to journalArticle

Logic synthesis and optimization methods for Sea-of-LUTs based PCA

Nagoya, A., Yamashita, S., Inamori, M. & Sawada, H., Jan 1 2000, In : NTT R and D. 49, 9, p. 537-545 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

SPFD: a new method to express functional flexibility

Yamashita, S., Sawada, H. & Nagoya, A., Aug 1 2000, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19, 8, p. 840-849 10 p.

Research output: Contribution to journalArticle

36 Citations (Scopus)
1998

An efficient method for finding an optimal bi-decomposition

Yamashita, S., Sawada, H. & Nagoya, A., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2529-2537 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
1 Citation (Scopus)

Restructuring logic representations with simple disjunctive decompositions

Sawada, H., Yamashita, S. & Nagoya, A., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2538-2544 7 p.

Research output: Contribution to journalArticle

1997

A hierarchical clustering method for the multiple constant multiplication problem

Matsuura, A., Yukishita, M. & Nagoya, A., Jan 1 1997, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 10, p. 1767-1773 7 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

Design automation technologies for realizing novel concurrent architecture

Nagoya, A., Dec 1 1997, In : NTT R and D. 46, 2, p. 153-158 6 p.

Research output: Contribution to journalArticle

Logic synthesis for look-up table based fpgas using functional decomposition and boolean resubstitution

Sawada, H., Suyama, T. & Nagoya, A., Jan 1 1997, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 1017-1023 7 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)
1987

DIPS-11/5E SERIES MAINFRAMES.

Shiokawa, S., Obashi, Y. & Nagoya, A., Nov 1 1987, In : Reports of the Electrical Communication Laboratory. 35, 6, p. 633-641 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

DIPS-11/5E SERIES PROCESSOR.

Shiokawa, S., Matsumoto, A., Nagoya, A. & Tajiri, K., Jan 1 1987, In : Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku. 36, 1, p. 57-65 9 p.

Research output: Contribution to journalArticle