• 302 Citations
  • 8 h-Index
1987 …2018
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Research Output 1987 2018

  • 302 Citations
  • 8 h-Index
  • 42 Article
  • 22 Conference contribution
  • 1 Chapter
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Conference contribution
2018

Acceleration of analysis processing on decentralized performance profiling system using virtual machines

Yamamoto, M., Nakashima, K., Yamauchi, T., Nagoya, A. & Taniguchi, H., Dec 26 2018, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 152-158 7 p. 8590889. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Virtual Machine
Profiling
Decentralized
Sampling
Processing
2003
1 Citation (Scopus)

Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture

Nakane, Y., Nagami, K., Shiozawa, T. & Nagoya, A., 2003, Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc., p. 136-143 8 p. 1275741

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable architectures
Computer operating systems
Virtualization
2001
7 Citations (Scopus)

Dynamically reconfigurable logic LSI - PCA-1

Ito, H., Konishi, R., Nakada, H., Oguri, K., Nagoya, A., Imlig, N., Nagami, K., Shiozawa, T. & Inamori, M., 2001, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. CIRCUITS SYMP. ed. p. 103-106 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Logic circuits
Computer architecture
34 Citations (Scopus)

PCA-1: A fully asynchronous, self-reconfigurable LSI

Konishi, R., Ito, H., Nakada, H., Nagoya, A., Oguri, K., Imlig, N., Shiozawa, T., Inamori, M. & Nagami, K., 2001, Proceedings - International Symposium on Asynchronous Circuits and Systems. p. 54-61 8 p. 914069

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Plastics
Networks (circuits)
Reconfigurable hardware
Scalability
Electric power utilization
2 Citations (Scopus)

Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture

Imlig, N., Shiozawa, T., Nagami, K., Nakane, Y., Konishi, R., Ito, H. & Nagoya, A., 2001, Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001. Institute of Electrical and Electronics Engineers Inc., p. 1441-1449 9 p. 925127

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Plastics
Processing
Networks (circuits)
Communication
Message passing
2 Citations (Scopus)

Self-reorganising systems on VLSI circuits

Nakada, H., Ito, H., Konishi, R., Nagoya, A., Oguri, K., Shiozawa, T. & Imlig, N., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 4. p. 310-313 4 p. 922234

Research output: Chapter in Book/Report/Conference proceedingConference contribution

VLSI circuits
Plastics
Telecommunication networks
2 Citations (Scopus)

Self-reorganising systems on VLSI circuits

Nakada, H., Ito, H., Konishi, R., Nagoya, A., Oguri, K., Shiozawa, T. & Imlig, N., 2001, Materials Research Society Symposium - Proceedings. Tritt, T. M., Nolas, G. S., Mahan, G. D. & Mandrus, D. (eds.). Vol. 626.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

VLSI circuits
Plastics
Telecommunication networks
2000
1 Citation (Scopus)

An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation

Yamashita, S., Sawada, H. & Nagoya, A., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 253-258 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition
Costs
3 Citations (Scopus)

An implementation of longest prefix matching for IP router on plastic cell architecture

Shiozawa, T., Imlig, N., Nagami, K., Oguri, K., Nagoya, A. & Nakada, H., 2000, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1896. p. 805-809 5 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Internet protocols
Prefix
Router
Routers
Plastics
8 Citations (Scopus)

A threshold logic-based reconfigurable logic element with a new programming technology

Aoyama, K., Sawada, H., Nagoya, A. & Nakajima, K., 2000, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1896. p. 665-674 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Threshold logic
Programming
Data Storage
Logic
Data storage equipment
1999

Integrated approach for synthesizing LUT networks

Yamashita, S., Sawada, H. & Nagoya, A., 1999, Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, p. 136-139 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition
3 Citations (Scopus)

Solving satisfiability problems on FPGAs using experimental unit propagation

Suyama, T., Yokoo, M. & Nagoya, A., 1999, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1713. p. 434-445 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1713).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Satisfiability Problem
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Propagation
Unit
3 Citations (Scopus)

Solving satisfiability problems on FPGAs using experimental unit propagation heuristic

Suyama, T., Yokoo, M. & Nagoya, A., 1999, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1586. p. 709-711 3 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1586).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Satisfiability Problem
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Logic circuits
Heuristics
1998
9 Citations (Scopus)

Restructuring logic representations with easily detectable simple disjunctive decompositions

Sawada, H., Yamashita, S. & Nagoya, A., 1998, Proceedings -Design, Automation and Test in Europe, DATE. p. 755-759 5 p. 655943

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition
Logic circuits
Cones
Experiments
1997
3 Citations (Scopus)

Efficient hierarchical clustering method for the multiple constant multiplication problem

Matsuura, A., Yukishita, M. & Nagoya, A., 1997, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, p. 83-88 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

High level synthesis
1 Citation (Scopus)

Formulation of the addition-shift-sequence problem and its complexity

Matsuura, A. & Nagoya, A., 1997, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1350. p. 43-51 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1350).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computational complexity
Formulation
Hardware
Integer
Hardware Implementation
2 Citations (Scopus)

Hardware/software codesign method for a general purpose reconfigurable co-processor

Kimura, S., Yukishita, M., Itou, Y., Nagoya, A., Hirao, M. & Watanabe, K., 1997, Hardware/Software Codesign - Proceedings of the International Workshop. Anon (ed.). p. 147-151 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer systems
System buses
Dynamic mechanical analysis
Field programmable gate arrays (FPGA)
Hardware
5 Citations (Scopus)

Restricted simple disjunctive decompositions based on grouping symmetric variables

Sawada, H., Yamashita, S. & Nagoya, A., 1997, Proceedings of the IEEE Great Lakes Symposium on VLSI. Anon (ed.). IEEE, p. 39-44 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition
Binary decision diagrams
Costs
1996

LUT-based FPGA technology mapping using permissible functions

Suyama, T., Sawada, H. & Nagoya, A., 1996, Proceedings of the IEEE International Conference on VLSI Design. IEEE, p. 215-218 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Combinatorial circuits
Boolean functions
Networks (circuits)
Experiments
50 Citations (Scopus)

New method to express functional permissibilities for LUT based FPGAs and its applications

Yamashita, S., Sawada, H. & Nagoya, A., 1996, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. Anon (ed.). IEEE, p. 254-261 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
1995
36 Citations (Scopus)

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

Sawada, H., Suyama, T. & Nagoya, A., 1995, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. Anon (ed.). IEEE, p. 353-358 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Decomposition
Logic Synthesis
1990
2 Citations (Scopus)

Multi-level logic optimization for large scale ASICs

Nagoya, A., Nakamura, Y., Oguri, K. & Nomura, R., 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 564-567 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Application specific integrated circuits
Networks (circuits)
Program processors
Computer aided design