• 305 Citations
  • 8 h-Index
1987 …2018

Research output per year

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Research Output

2004

Dynamically reconfigurable logic LSI: PCA-2

Ito, H., Konishi, R., Nakada, H., Tsuboi, H., Okuyama, Y. & Nagoya, A., Aug 2004, In : IEICE Transactions on Information and Systems. E87-D, 8, p. 2011-2020 10 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

PARTHENONの概要

Nagoya, A., 2004, In : 第12回PARTHENON講習会テキスト. p. 85-96 12 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2004, In : 第12回PARTHENON講習会テキスト. p. 97-122 26 p.

Research output: Contribution to journalArticle

2005

PARTHENONの概要

Nagoya, A., 2005, In : 第12回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2005, In : 第12回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

2006

PARTHENONの概要

Nagoya, A., 2006, In : 第14回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2006, In : 第14回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

自律再構成可能アーキテクチャPCAの構成手法

Nagoya, A., 2006, In : 電子情報通信学会論文誌 D. J89-D, 6, p. 1110-1119 10 p.

Research output: Contribution to journalArticle

2007

Network processor for high-speed network and quick programming

Murooka, T., Nagoya, A., Miyazaki, T., Ochi, H. & Nakamura, Y., Feb 1 2007, In : Journal of Circuits, Systems and Computers. 16, 1, p. 65-79 15 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2007, In : 第15回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2007, In : 第15回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

2008

PARTHENONの概要

Nagoya, A., 2008, In : 第16回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2008, In : 第16回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

2011

PARTHENONの概要

Nagoya, A., 2011, In : 第17回PARTHENON講習会資料(CD-R). p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2011, In : 第17回PARTHENON講習会資料(CD-R). p. 1-24 24 p.

Research output: Contribution to journalArticle

2018

Acceleration of analysis processing on decentralized performance profiling system using virtual machines

Yamamoto, M., Nakashima, K., Yamauchi, T., Nagoya, A. & Taniguchi, H., Dec 26 2018, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 152-158 7 p. 8590889. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution