• 305 Citations
  • 8 h-Index
1987 …2018

Research output per year

If you made any changes in Pure these will be visible here soon.

Research Output

Acceleration of analysis processing on decentralized performance profiling system using virtual machines

Yamamoto, M., Nakashima, K., Yamauchi, T., Nagoya, A. & Taniguchi, H., Dec 26 2018, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 152-158 7 p. 8590889. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A general framework to use various decomposition methods for LUT network synthesis

Yamashita, S., Sawada, H. & Nagoya, A., Nov 2001, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2915-2922 8 p.

Research output: Contribution to journalArticle

A hierarchical clustering method for the multiple constant multiplication problem

Matsuura, A., Yukishita, M. & Nagoya, A., Jan 1 1997, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 10, p. 1767-1773 7 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

A method of mapping finite state machine into PCA plastic parts

Inamori, M., Nakada, H., Konishi, R., Nagoya, A. & Oguri, K., Apr 2002, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 4, p. 804-810 7 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation

Yamashita, S., Sawada, H. & Nagoya, A., Dec 1 2000, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 253-258 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An efficient implementation method of fractal image compression on dynamically reconfigurable architecture

Nagano, H., Matsuura, A. & Nagoya, A., Jan 1 1999, Parallel and Distributed Processing - 11 th IPPS/SPDP 1999 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing, Proceedings. Rolim, J. (ed.). Springer Verlag, p. 670-678 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1586).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

An efficient method for finding an optimal bi-decomposition

Yamashita, S., Sawada, H. & Nagoya, A., Jan 1 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2529-2537 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A new notion for functional flexibility: A summary

Yamashita, S., Sawada, H. & Nagoya, A., Dec 1 2002, In : IEEE Circuits and Systems Magazine. 2, 2, p. 52-54 3 p.

Research output: Contribution to journalArticle

An implementation of longest prefix matching for IP router on plastic cell architecture

Shiozawa, T., Imlig, N., Nagami, K., Oguri, K., Nagoya, A. & Nakada, H., 2000, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing - 10th International Conference, FPL 2000, Proceedings. Hartenstein, R. W. & Grunbacher, H. (eds.). Springer Verlag, p. 805-809 5 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Asynchronous bit-serial datapath for object-oriented reconfigurable architecture PCA

Oguri, K., Shibata, Y. & Nagoya, A., 2003, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Omondi, A. & Sedukhin, S. (eds.). Springer Verlag, p. 54-68 15 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2823).

Research output: Chapter in Book/Report/Conference proceedingChapter

A threshold logic-based reconfigurable logic element with a new programming technology

Aoyama, K., Sawada, H., Nagoya, A. & Nakajima, K., Jan 1 2000, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing - 10th International Conference, FPL 2000, Proceedings. Grunbacher, H. & Hartenstein, R. W. (eds.). Springer Verlag, p. 665-674 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)
1 Citation (Scopus)

Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture

Nakane, Y., Nagami, K., Shiozawa, T. & Nagoya, A., Jan 1 2003, Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc., p. 136-143 8 p. 1275741. (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Concept of the Plastic Cell Architecture (PCA)

Nagoya, A. & Oguri, K., Jan 1 2000, In : NTT R and D. 49, 9, p. 513-517 5 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Design automation technologies for realizing novel concurrent architecture

Nagoya, A., Dec 1 1997, In : NTT R and D. 46, 2, p. 153-158 6 p.

Research output: Contribution to journalArticle

DIPS-11/5E SERIES MAINFRAMES.

Shiokawa, S., Obashi, Y. & Nagoya, A., Nov 1 1987, In : Reports of the Electrical Communication Laboratory. 35, 6, p. 633-641 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

DIPS-11/5E SERIES PROCESSOR.

Shiokawa, S., Matsumoto, A., Nagoya, A. & Tajiri, K., Jan 1 1987, In : Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku. 36, 1, p. 57-65 9 p.

Research output: Contribution to journalArticle

Dynamically reconfigurable logic LSI: PCA-2

Ito, H., Konishi, R., Nakada, H., Tsuboi, H., Okuyama, Y. & Nagoya, A., Aug 2004, In : IEICE Transactions on Information and Systems. E87-D, 8, p. 2011-2020 10 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

Dynamically Reconfigurable Logic LSI designed as Fully Asynchronous System - PCA-2

Nagoya, A., 2003, In : Proc. of COOL Chips VI. p. 84-84 1 p.

Research output: Contribution to journalArticle

Dynamically reconfigurable logic LSI - PCA-1

Ito, H., Konishi, R., Nakada, H., Oguri, K., Nagoya, A., Imlig, N., Nagami, K., Shiozawa, T. & Inamori, M., Jan 1 2001, p. 103-106. 4 p.

Research output: Contribution to conferencePaper

7 Citations (Scopus)

Dynamically Reconfigurable Logic LSI - PCA-1: The First Realization of the Plastic Cell Architecture

Ito, H., Konishi, R., Nakada, H., Oguri, K., Inamori, M. & Nagoya, A., May 2003, In : IEICE Transactions on Information and Systems. E86-D, 5, p. 859-867 9 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

Efficient hierarchical clustering method for the multiple constant multiplication problem

Matsuura, A., Yukishita, M. & Nagoya, A., Jan 1 1997, p. 83-88. 6 p.

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Efficient kernel generation based on implicit cube set representations and its applications

Sawada, H., Yamashita, S. & Nagoya, A., Dec 1 2000, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2513-2519 7 p.

Research output: Contribution to journalArticle

Formulation of the addition-shift-sequence problem and its complexity

Matsuura, A. & Nagoya, A., 1997, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1350. p. 43-51 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1350).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Hardware/software codesign method for a general purpose reconfigurable co-processor

Kimura, S., Yukishita, M., Itou, Y., Nagoya, A., Hirao, M. & Watanabe, K., Jan 1 1997, p. 147-151. 5 p.

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Integrated approach for synthesizing LUT networks

Yamashita, S., Sawada, H. & Nagoya, A., Dec 1 1999, Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, p. 136-139 4 p. (Proceedings of the IEEE Great Lakes Symposium on VLSI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Logic synthesis and optimization methods for Sea-of-LUTs based PCA

Nagoya, A., Yamashita, S., Inamori, M. & Sawada, H., Jan 1 2000, In : NTT R and D. 49, 9, p. 537-545 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Logic synthesis for look-up table based fpgas using functional decomposition and boolean resubstitution

Sawada, H., Suyama, T. & Nagoya, A., Jan 1 1997, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 1017-1023 7 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)
38 Citations (Scopus)

LUT-based FPGA technology mapping using permissible functions

Suyama, T., Sawada, H. & Nagoya, A., Jan 1 1996, p. 215-218. 4 p.

Research output: Contribution to conferencePaper

Multi-level logic optimization for large scale ASICs

Nagoya, A., Nakamura, Y., Oguri, K. & Nomura, R., Dec 1 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 564-567 4 p. (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Network processor for high-speed network and quick programming

Murooka, T., Nagoya, A., Miyazaki, T., Ochi, H. & Nakamura, Y., Feb 1 2007, In : Journal of Circuits, Systems and Computers. 16, 1, p. 65-79 15 p.

Research output: Contribution to journalArticle

New methods to find optimal non-disjoint bi-decompositions

Yamashita, S., Sawada, H. & Nagoya, A., Dec 1 1998, p. 59-68. 10 p.

Research output: Contribution to conferencePaper

16 Citations (Scopus)

New method to express functional permissibilities for LUT based FPGAs and its applications

Yamashita, S., Sawada, H. & Nagoya, A., Dec 1 1996, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 254-261 8 p.

Research output: Contribution to journalConference article

51 Citations (Scopus)

PARTHENONの概要

Nagoya, A., 2007, In : 第15回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2008, In : 第16回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2011, In : 第17回PARTHENON講習会資料(CD-R). p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2002, In : 第10回PARTHENON講習会テキスト. p. 3-14 12 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2005, In : 第12回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2003, In : 第11回PARTHENON講習会テキスト. p. 129-140 12 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2004, In : 第12回PARTHENON講習会テキスト. p. 85-96 12 p.

Research output: Contribution to journalArticle

PARTHENONの概要

Nagoya, A., 2006, In : 第14回PARTHENON講習会テキスト. (CD-ROM), p. 1-10 10 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2004, In : 第12回PARTHENON講習会テキスト. p. 97-122 26 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2011, In : 第17回PARTHENON講習会資料(CD-R). p. 1-24 24 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2005, In : 第12回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2008, In : 第16回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2007, In : 第15回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle

PARTHENONの論理回路最適化プログラムの利用技法

Nagoya, A., 2006, In : 第14回PARTHENON講習会テキスト. (CD-ROM), p. 1-24 24 p.

Research output: Contribution to journalArticle